Performance and Power Analysis of Routing Algorithms on NOC

Network-on-Chip (NOC) has been proposed as an attractive alternative to traditional dedicated wire to achieve high performance and modularity. Power efficiency is the most important concern in NOC design. Routing algorithms have major effect on power and performance. We have implemented an accurate meshbased hardware model for NOC with VHDL and using it, have measured the performance and power in several routing algorithms. The effect of number of virtual channels on power and performance of NoC has also been studied. Moreover we have considered the effect of single fault in load and packet misrouting of these algorithms. We also have synthesized these routing algorithms on FPGA to estimate power of each algorithm. key words: Network on Chip , Routing Algorithm, Fault, Power, Performance, Interconnection Network.